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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Answered

    cortex a53 : How to detect cached data is invalid ? (use ddr memory) 0

    • Cache Controllers
    • Cache Management
    7706 views
    4 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Answered

    some question about ACE 0

    • ACE
    4269 views
    3 replies
    Latest over 4 years ago
    by vstehle Arm Employee Badge
  • Suggested Answer

    Why does the assembly code sometimes store the register values into RAM and sometimes not? 0

    • Arm Assembly Language (ASM)
    • Arm Compiler 5
    3761 views
    5 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    STR instruction fails in Assembly 0

    • Arm Assembly Language (ASM)
    2345 views
    0 replies
    Started over 4 years ago
    by Cantaff0rd
  • Not Answered

    Recursive Fibonacci sequence on M4 - improving the code 0

    • Arm Assembly Language (ASM)
    4161 views
    1 reply
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    Code alignment significantly affecting performance? 0

    3494 views
    7 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    Cortex-M55 LDRx instructions 0

    • Cortex-M55
    • Arm Assembly Language (ASM)
    2350 views
    4 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    Cortex M0+ Problems using MPU + SVC Call 0

    • Cortex-M0+
    • 11 (SVCall)
    1317 views
    0 replies
    Started over 4 years ago
    by riglesias
  • Not Answered

    Bare metal startup code for Cortex-78 CPUs 0

    4221 views
    6 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    execution fault after enabling mpu 0

    • Cortex-M23
    • 3 (HardFault)
    2020 views
    1 reply
    Latest over 4 years ago
    by 42Bastian Schick
  • Answered

    Taking exceptions from EL1 to EL1: Problems with SVC 0

    • Cortex-A53
    • AArch64
    • ARMv8 Exception Model
    8779 views
    12 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Answered

    SMMU: Why do the software in EL1 can modify the TTB of S2 in stream table entry when stage 2 is enabled? 0

    4500 views
    6 replies
    Latest over 4 years ago
    by 林军
  • Not Answered

    Difference between SP_EL1 and SPSEL + MOV 0

    5281 views
    6 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    physical and virtual timer. 0

    3851 views
    2 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    LPC 2148 Push Button interrupt problem 0

    • Keil C51 Dev Tools
    4505 views
    4 replies
    Latest over 4 years ago
    by LoriePetty
  • Answered

    Virtual interrupt EOI mode & irq state 0

    • GICv2
    • GICv3/v4
    • virtualization
    5939 views
    3 replies
    Latest over 4 years ago
    by HenryW1991
  • Suggested Answer

    MPU region size halved 0

    1710 views
    2 replies
    Latest over 4 years ago
    by kiko
  • Not Answered

    Why there is no layer like CMSIS for Cortex R ? 0

    3070 views
    3 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Answered

    Partial cache line store in ACE protocol 0

    3721 views
    3 replies
    Latest over 4 years ago
    by vstehle Arm Employee Badge
  • Answered

    Arm cortex a53 giving abort when mmu is enabled and reading data from device region 0

    • Cortex-A53
    • Memory Management Unit (MMU)
    6740 views
    8 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
<>
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