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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3601 Questions
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  • Not Answered

    Cortex-M0+ core Hang up in FFFF FFFEh address when executing DSB instruction. 0

    • Real Time Operating Systems (RTOS)
    • 3 (HardFault)
    • Cortex-M0+
    9560 views
    1 reply
    Latest over 5 years ago
    by Robert Wolff
  • Not Answered

    Early Burst Termination with IDLE transfer in Multi-Layer AHB Lite 0

    12753 views
    8 replies
    Latest over 5 years ago
    by Guy H
  • Not Answered

    Converting C into M0+ 0

    2935 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    M7 compilation with xcelium 0

    2406 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    CMSIS and GPIO 0

    2536 views
    0 replies
    Started over 5 years ago
    by Silicium
  • Answered

    UART + DMA: how to ? 0

    8886 views
    6 replies
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    IMPRECISERR on Cortex-M33 r0p3 0

    • Documentation
    • Cortex-M33
    2230 views
    0 replies
    Started over 5 years ago
    by Zbynek Mynar
  • Not Answered

    Strange M0+ instruction format 0

    2290 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    Why I'm not able to put the breakpoints?? 0

    4032 views
    4 replies
    Latest over 5 years ago
    by omkardixi
  • Not Answered

    Interrupt latency while STR/LDR in cortex-M3 0

    2637 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    Cortex M7 SPI Interface Register Base Address 0

    • Cortex-M7
    6154 views
    6 replies
    Latest over 5 years ago
    by atlasium47
  • Answered

    why there are separate registers for interrupt set-enable and clear-enable while can be just one 0

    • Cortex-M3
    • Cortex-M System Design Kit
    5033 views
    2 replies
    Latest over 5 years ago
    by Morteza
  • Not Answered

    Does Cortex-M33/M35P support bit band? 0

    • Cortex-M35P
    • Cortex-M33
    • Armv8-M
    • Memory Architecture
    3132 views
    0 replies
    Started over 5 years ago
    by zhyihui2100
  • Answered

    JTAG Debugger for Cortex-R7 0

    4642 views
    3 replies
    Latest over 5 years ago
    by shubham@p
  • Answered

    Bus Fault when configuring cross trigger matrix / CTICONTROL 0

    3726 views
    2 replies
    Latest over 5 years ago
    by Jacek Wywrót
  • Not Answered

    SAMD21G18A Controller,s Bootloader Delete after program with Arduino IDE 0

    2966 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Answered

    Why is there an ACP interface for many ARM processors? 0

    • AXI
    35983 views
    8 replies
    Latest over 5 years ago
    by marekx
  • Not Answered

    ETM Trace bus signal integrity 0

    • ETM
    1848 views
    0 replies
    Started over 5 years ago
    by Chandrasekar J
  • Not Answered

    Cortex A-35 prevent fetch code allocation in cache 0

    11761 views
    4 replies
    Latest over 5 years ago
    by flongnos
  • Not Answered

    What conditions would generate the CM33 FPU underflow and input denormal exception flags? 0

    • Cortex-M33
    2062 views
    0 replies
    Started over 5 years ago
    by Ankur B
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