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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3593 Questions
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  • Answered

    How to access memory more than 4GB by using 32bit ISA? +1

    • Memory Access Instructions
    7603 views
    4 replies
    Latest over 5 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Saving processor state for power-down and resume 0

    • Thumb
    • Cortex-M4
    4710 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Pros and cons of activating cache in stm32F7 0

    4052 views
    0 replies
    Started over 5 years ago
    by Marzi
  • Not Answered

    making physical memory pages not cacheable (probabaly by modifying page table entry) 0

    20419 views
    0 replies
    Started over 5 years ago
    by Gol
  • Not Answered

    Debug Connection Cause ExecutionTiming Problem on Second Core of Cortex A9 on Zynq 702 MPCore 0

    • System on Chip (SoC)
    • Cortex-A9
    22337 views
    3 replies
    Latest over 5 years ago
    by BurakSeker
  • Not Answered

    flush_cache_all() API consuming 200+ microseconds. 0

    21358 views
    4 replies
    Latest over 5 years ago
    by vaiyawa
  • Answered

    R5 vs A9 Performances +1

    • Cortex-A9
    • Cortex-R5
    13107 views
    9 replies
    Latest over 5 years ago
    by Poz1
  • Suggested Answer

    Where can I apply for cortex m0/m3 IP with GDSII files 0

    3027 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    Is it typical at least 2 cycles taken for load from and store to a zero wait state accessible memory? 0

    • Memory Access Instructions
    4444 views
    4 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    Address memory of the next instruction in A9 MPCore 0

    • R15 (PC Program Counter)
    21792 views
    3 replies
    Latest over 5 years ago
    by dVaquerizo
  • Answered

    How to flush write buffer when memory attribute is normal_nc 0

    • Cache coherency
    26253 views
    4 replies
    Latest over 5 years ago
    by bamvor2022
  • Answered

    ARM R5 and A53 cores coexist +1

    26754 views
    2 replies
    Latest over 5 years ago
    by Stuart Hirons Arm Employee Badge
  • Not Answered

    Hard fault : Cortex M0+ platform. 0

    • Cortex-M0+
    4795 views
    4 replies
    Latest over 5 years ago
    by Tejeshwar
  • Answered

    Is a MOV using high registers (R8-R15) possible with the ARMv6-M architecture? 0

    • Armv6-M
    • Documentation
    5074 views
    3 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    How to test atomic access implemented with Load Store Exclusive Assembly (LDREX / STREX) 0

    • Cortex-M4
    4316 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Invalid state usage fault( INVSTATE ) for arm instruction 0

    11851 views
    2 replies
    Latest over 5 years ago
    by anoop
  • Not Answered

    The "usage model" of ARMv8 SVE contiguous "non-fault" load instructions ? 0

    • Armv8-A
    22848 views
    2 replies
    Latest over 5 years ago
    by alexn
  • Not Answered

    How to do from Secure(EL3) to Non-secure Exception level transition in ARMV8-A ? +1

    • EL1
    • EL3
    • EL2
    • AArch64
    • ARMv8 Exception Model
    28443 views
    4 replies
    Latest over 5 years ago
    by Mr_Sanjay
  • Suggested Answer

    Partial register dependency neon 0

    • Cortex-A57
    • AArch64
    • optimization
    • NEON
    28580 views
    4 replies
    Latest over 5 years ago
    by doofenstein
  • Not Answered

    Building Ne10 Library With ArmCompiler 5 on ARM Cortex A9 0

    • Arm Compiler 6
    • Cortex-A9
    • NEON
    • Arm Compiler 5
    18976 views
    0 replies
    Started over 5 years ago
    by BurakSeker
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