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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3592 Questions
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  • Answered

    Understanding interrupt latency and jitter in Cortex-M 0

    • Interrupt Handling
    • Cortex-M7
    • Cortex-M
    • Interrupt
    13143 views
    7 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Suggested Answer

    ARM M0 and M3 0

    2865 views
    2 replies
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    Problems with DSP course 0

    1397 views
    0 replies
    Started over 5 years ago
    by goldenthyme
  • Answered

    ID issue 0

    13212 views
    2 replies
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Use keil5 to compile AM335X +1

    13003 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Suggested Answer

    How many clock cycles does a"for" loop take? 0

    13579 views
    5 replies
    Latest over 5 years ago
    by WestfW
  • Answered

    DWT instruction address 0

    • CoreSight Debug and Trace
    • Cortex-M33
    • Armv8-M
    3700 views
    2 replies
    Latest over 5 years ago
    by Lica
  • Not Answered

    cortex M33 multicore debug resources 0

    2860 views
    3 replies
    Latest over 5 years ago
    by Sinie
  • Not Answered

    Reading Non-Secure PENDSVSET after re-entry into Secure PendSV 0

    3001 views
    2 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    About the snoop filter in CCI 550 0

    • Cache coherency
    • CoreLink CCI-550 Cache Coherent Interconnect
    13322 views
    0 replies
    Started over 5 years ago
    by zilly
  • Answered

    Cortex-A53 direct access to cache: How are instructions encoded in the L1 I-cache? 0

    • Cortex-A53
    • Cache
    • Cortex-A
    22460 views
    4 replies
    Latest over 5 years ago
    by zilly
  • Not Answered

    DRAM address mapping on a Cortex-A72 ARMv8 0

    • Cortex-A72
    • Armv8-A
    13616 views
    2 replies
    Latest over 5 years ago
    by Frederick
  • Answered

    Running armv7 binaries on armv8 0

    • Armv7-A
    • Armv8-A
    46396 views
    8 replies
    Latest over 5 years ago
    by Cyan101
  • Not Answered

    Which PMU Events for L2 Cache Misses on Cortex-A72 0

    15241 views
    2 replies
    Latest over 5 years ago
    by John Duffy
  • Not Answered

    Reading analog pin while boundary scanning 0

    • JTAG
    • Cortex-M4
    • CoreSight ETM-M4
    5134 views
    7 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    A low-overhead real time counter consistent cross processor cores 0

    25330 views
    2 replies
    Latest over 5 years ago
    by zilly
  • Not Answered

    Cortex A9 MMU 0

    25444 views
    17 replies
    Latest over 5 years ago
    by deas
  • Not Answered

    QSPI out of space Musca board 0

    • Source code
    • Musca-A
    • TrustZone
    2710 views
    1 reply
    Latest over 5 years ago
    by Lica
  • Not Answered

    Decoding the DRAM addressing from AXI byte addressing on PS side of ARM Cortex A53 0

    14805 views
    0 replies
    Started over 5 years ago
    by fpga123
  • Not Answered

    Memory profiling (ARM Musca A1 Board) 0

    • Musca-A
    • CoreLink SSE-200 Subsystem for Embedded
    • Cortex-M33
    • Memory
    1590 views
    0 replies
    Started over 5 years ago
    by Lica
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone