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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
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  • Not Answered

    Is it possible to turn my phone's 64-bit armv8-a (32-bit mode) to 64 bit mode 0

    24088 views
    1 reply
    Latest over 5 years ago
    by Raheem
  • Not Answered

    Cortex-R52 data cache content 0

    • Cortex-R5
    • Cache
    3161 views
    1 reply
    Latest over 5 years ago
    by Elnora
  • Not Answered

    Interrupts not received in secure world for Cortex A7 in Trsuty 0

    • Arm Trusted Firmware
    • Cortex-A7
    8613 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    CMSIS5: Matrix assignment doesn't work in my code. How to debug? 0

    • Digital Signal Processor (DSP)
    • CMSIS
    • Cortex-M4
    2592 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    Why don't we see 8+ Cortex A77 cores in a cheap desktop device? Are there driver issues with Linux for such a device? 0

    9559 views
    1 reply
    Latest over 5 years ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    ARM way how to handle and generate own run time error, like try raise catch 0

    2055 views
    0 replies
    Started over 5 years ago
    by Silicium
  • Not Answered

    Exception Level Switch in ARMv8 0

    10347 views
    2 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Time measurements ARM v8 platform running Linux 0

    • Cortex-A72
    • Armv8-A
    11351 views
    2 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Is it possible to implement global platform API on trusted firmware-m 0

    • Cortex-M23
    • Platform Security Architecture (PSA)
    • Trusted Execution Environment (TEE)
    2392 views
    1 reply
    Latest over 5 years ago
    by Robert Wolff
  • Not Answered

    Generate Assembly Code for ODROID-XU4 0

    9525 views
    1 reply
    Latest over 5 years ago
    by Robert Wolff
  • Not Answered

    Cortex-M0+ core Hang up in FFFF FFFEh address when executing DSB instruction. 0

    • Real Time Operating Systems (RTOS)
    • 3 (HardFault)
    • Cortex-M0+
    9510 views
    1 reply
    Latest over 5 years ago
    by Robert Wolff
  • Not Answered

    Early Burst Termination with IDLE transfer in Multi-Layer AHB Lite 0

    12617 views
    8 replies
    Latest over 5 years ago
    by Guy H
  • Not Answered

    Converting C into M0+ 0

    2907 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    M7 compilation with xcelium 0

    2389 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    CMSIS and GPIO 0

    2507 views
    0 replies
    Started over 5 years ago
    by Silicium
  • Answered

    UART + DMA: how to ? 0

    8774 views
    6 replies
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    IMPRECISERR on Cortex-M33 r0p3 0

    • Documentation
    • Cortex-M33
    2207 views
    0 replies
    Started over 5 years ago
    by Zbynek Mynar
  • Not Answered

    Strange M0+ instruction format 0

    2269 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    Why I'm not able to put the breakpoints?? 0

    3981 views
    4 replies
    Latest over 5 years ago
    by omkardixi
  • Not Answered

    Interrupt latency while STR/LDR in cortex-M3 0

    2591 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
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