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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3590 Questions
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  • Answered

    Inner/Outer Cacheability in Cortex V8-R +1

    8665 views
    4 replies
    Latest over 4 years ago
    by XNoOp
  • Not Answered

    how to connect the ACP (accelerate coherence port) interface with my SoC system 0

    1853 views
    0 replies
    Started over 4 years ago
    by chenyu
  • Not Answered

    What happens if NMI is triggered while processing an existing NMI? 0

    • 2 (NMI)
    • Interrupt Handling
    • Cortex-M7
    2553 views
    2 replies
    Latest over 4 years ago
    by Robert McNamara
  • Answered

    How is AHB faster than APB? The transfer will be a normal single transfer. 0

    19918 views
    5 replies
    Latest over 4 years ago
    by Manjuja
  • Not Answered

    Loadind PDSC Debug Destryption failed for STM32L010 0

    2613 views
    5 replies
    Latest over 4 years ago
    by slawek krzysiek
  • Not Answered

    [M0+] Get CONTROL register on HardFault Handler 0

    • 3 (HardFault)
    • Cortex-M0+
    1597 views
    0 replies
    Started over 4 years ago
    by riglesias
  • Not Answered

    Can multiple cores perform L2 cache maintenance operations to flush (say) different addresses from the L2 cache. 0

    2768 views
    0 replies
    Started over 4 years ago
    by conradomaher
  • Answered

    _Min_Heap_Size and _Min_Stack_Size 0

    2702 views
    2 replies
    Latest over 4 years ago
    by Gknr
  • Not Answered

    I had some problems downloading Cortex-M0 DesignStart Eval. 0

    1127 views
    0 replies
    Started over 4 years ago
    by Weskiey
  • Suggested Answer

    AXI slave design and verification 0

    6844 views
    10 replies
    Latest over 4 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Custom bootable image 0

    3903 views
    2 replies
    Latest over 4 years ago
    by segfault
  • Answered

    MULSHIFT32 in 14 cycles 0

    4362 views
    10 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    Flushing the data cache in arm-trusted-firmware 0

    • Cortex-A53
    • Arm Trusted Firmware
    • Armv8-A
    5834 views
    3 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Answered

    In ARM7 and ARM9 PC=current + 8, but in the cortex-A7(8-stage pipeline) the PC is also the same value(PC=current +8), how does this work? 0

    • Arm7
    • Arm9
    • Armv8-A
    • Cortex-A
    • Cortex-A7
    7056 views
    3 replies
    Latest over 4 years ago
    by Takahashi842
  • Not Answered

    is there CPS instruction alternatives to jump from EL1 to EL0 at boot time? 0

    • Cortex-R52
    3566 views
    7 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    IN AXI DATA INTERLEAVING HOW WID AND RID WILL CHANGE? 0

    • AMBA 3 AXI Interface
    • AXI
    • wifi
    5014 views
    2 replies
    Latest over 4 years ago
    by NEEL SHAH
  • Not Answered

    R52 , priority level = 31 : what is the expected behavior? 0

    • Cortex-R52
    • Interrupt Handling
    • Generic Interrupt Controller
    1365 views
    0 replies
    Started over 4 years ago
    by kduplantier
  • Answered

    TCM interface timing of Arm Cortex-r4f 0

    4791 views
    11 replies
    Latest over 4 years ago
    by Aaliyah
  • Not Answered

    how to use TCM interface of Arm Cortex-r4f 0

    2422 views
    2 replies
    Latest over 4 years ago
    by Aaliyah
  • Answered

    TF-M, how to sign an image.bin in a multi-image configuration? 0

    • Trusted Firmware-M
    • Cortex-M33
    3732 views
    1 reply
    Latest over 4 years ago
    by Cristiano_Ro
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