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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3629 Questions
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  • Not Answered

    cm7 and cm4 comparison 0

    2718 views
    1 reply
    Latest over 6 years ago
    by Pallavi boreddy
  • Answered

    obtaining cycle count on cortex m7 0

    7583 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    M4 Deep Sleep 0

    • STM32 F4
    5764 views
    2 replies
    Latest over 6 years ago
    by AliRizaDenenPezevenk
  • Answered

    Permission fault, level 2 on MMU enable 0

    • EL1
    • Armv8-A
    • Memory Management Unit (MMU)
    24659 views
    1 reply
    Latest over 6 years ago
    by a.surati
  • Not Answered

    Changing prio of running IRQ triggers hardfault 0

    • Armv7-M
    • Cortex-M4
    • Interrupt
    2702 views
    0 replies
    Started over 6 years ago
    by Vinci
  • Not Answered

    Cortex-M4 0

    2439 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Does MSR DAIF require ISB instruction? If no, why? 0

    • AArch64
    • Armv8-A
    25710 views
    2 replies
    Latest over 6 years ago
    by scopichmu
  • Not Answered

    Hart-i910 , what's real name of that MCU? 0

    4518 views
    3 replies
    Latest over 6 years ago
    by Andy Neil
  • Suggested Answer

    Tollchain for Cortex_M3 0

    2859 views
    1 reply
    Latest over 6 years ago
    by d.ry
  • Answered

    ACE MakeUnique Transaction 0

    22055 views
    2 replies
    Latest over 6 years ago
    by RajaAC
  • Not Answered

    What is the power consumption of a76 gpu and a77 gpu in normal state? 0

    • Cortex-A77
    • Cortex-A76
    20022 views
    0 replies
    Started over 6 years ago
    by Little_lan
  • Answered

    What can cause getting Cortex-A55 DSU P-Channel PACCEPT/PDENY signals fail? +1

    • Cortex-A55
    • Armv8-A
    • Cortex-A
    24650 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    MMU attributes implications on memory bandwidth +1

    23455 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    How to start cpu in ARMv7 baremetal environment? 0

    • Multiprocessor
    • Armv7-A
    • SMCCC
    22422 views
    4 replies
    Latest over 6 years ago
    by Levente
  • Answered

    how to handle lockup state in M33 +1

    14901 views
    14 replies
    Latest over 6 years ago
    by d.ry
  • Not Answered

    Cortex-M CMSIS Driver groups and related question 0

    • CMSIS
    3187 views
    0 replies
    Started over 6 years ago
    by d.ry
  • Not Answered

    Can code compiled for armv7-m run as it is on armv8-m? 0

    4421 views
    2 replies
    Latest over 6 years ago
    by Muhammad Usama Anjum
  • Not Answered

    How to write values ​​from secure code to non-secure memory. 0

    • TrustZone for Armv8-M
    10832 views
    1 reply
    Latest over 6 years ago
    by Uma Ramalingam Arm Employee Badge
  • Not Answered

    Overlapping the execution of VDIV.F32 and SDIV/UDIV 0

    3334 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Advantage of Zero register over the cost of implementing it ? +1

    • AArch64
    • Armv8-A
    • Cortex-A
    29477 views
    2 replies
    Latest over 6 years ago
    by Morgan CHANG
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