Hi,
Im new to ARM. Im learning generic timers in cortex a-53. I wanted to know whats the meaning of "system level implementation" of Generic Timer and "PE implementations" of the Generic Timer. How is it different from Generic timer in "AArch 64 State" ?
The term 'system' in the phrase 'system level implementation of the generic timer' points to the SoC, as contrasted with the Core/PE.
The term 'system' in the phrase 'system level architecture' points to the OS/kernel, as contrasted with an application (as in the application level architecture).
The term 'aarch64' in the phrase 'generic timer in aarch64 state' is to be contrasted with the term 'aarch32' in the phrase 'generic timer in aarch32 state'.
The Generic Timer needs certain components implemented at the SoC-level. These are accessible over a memory-mapped interface, as opposed to a (faster) PE-interface such as MRC/MCR/MRS/MSR. The 'system level implementation of the generic timer' provides information on these components and their interface.
Depending on the state (aarch64 or aarch32) in which the code, which accesses the timer components, is to be run, the related pieces of information should help in implementing it.
I am not sure about the phrase "PE Implementation". It might mean the per-PE/per-Core components and the interfaces, which are required to support the generic timer functionality on a per-Core basis. For e.g. CNTFRQ_EL0 is available on each Core, accessible through the MRC/MCR/MRS/MSR interface; a kernel sets it (for e.g through MSR) to the value read from the memory-mapped register CNTFID0.
Edit: Replace CPU with Core. Certain terms, such as PE, have specific definitions, and the ARM ARM is a good source to resolve them.
Thanks