cortex-m0 address branching from ROM to RAM

I'm designing a MCU platform that is using ROM and RAM.

My boot up scenario is as follows.

First, ROM F/W is executed after power up(ROM F/W is excecuted only 1 time).

And then, core waits for until program counter jump flag goes high at the end of ROM F/W

When program counter jump flag goes high, core PC jumps to the RAM region, and executes RAM F/W.

To operate above scenario, I'm trying to implement F/W code.

// sram_main();
 while(ready_SRAM == 1);  
 
  __asm  { B    0x00002000; }
 

I thought I could insert inline assembly in the code lik above, but I got an error like below.

Error:  #1113: Inline assembler not permitted when generating Thumb code

I found the resolution in the ARM information Center as below. But it doesn't work for my case.

//

If you want to include inline assembly in code to be compiled for Thumb, enclose the functions containing inline assembler code between #pragma arm and #pragma thumb statements (see Pragmas controlling code generation). For example:

#pragma arm
int add(int i, int j) {
    int res;
    __asm {
        ADD   res, i, j   // add here
    }
    return res;
}
#pragma thumb
//
Does anyone know to insert inline assembly in code to be compiled for Thumb code? 
or how can I make F/W which core program counter can jump from ROM to RAM?

Thank you.