ARM Cortex A9 - Enabling/Disabling the Caches

Hello,

I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9).

In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches, MMU and Program Prediction.

What I need is to know is if the following sequence is ok, or if I need to add more step (Like invalidating the caches ... etc.)

1. Enable the Caches, MMU and Program Prediction:

mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #ARM_CTRL_ICACHE
orr r0, r0, #ARM_CTRL_DCACHE
orr r0, r0, #ARM_FLOW_PREDICT
orr r0, r0, #ARM_MMU_ENABLE
mcr p15, 0, r0, c1, c0, 0

2. In a loop, initialize the ~50 MB

3. Disable the Caches, MMU and Program Prediction (It's a constrain from the OS):

mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #ARM_CTRL_ICACHE
bic r0, r0, #ARM_CTRL_DCACHE
bic r0, r0, #ARM_FLOW_PREDICT
bic r0, r0, #ARM_MMU_ENABLE
mcr p15, 0, r0, c1, c0, 0

4. Branch to the OS, it will later enable the Caches and MMU again at some point in its initialization sequence.

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Is this enough? Or I need to invalidate the caches at any point? Or need to adjust the order of enable/disable.

Thank you.