I don't have much experience in building an embedded system from 0. I want to ask a general question as showed in the title through an example.
I choose Cortex-A9 (ARMv7-Profile A architecture) as CPU. Then I want to use DDR3 RAM of Alliance memory (AS4C128M16D3B-12BCN) or ISSI
(IS43/46TR82560B). Question1: How to know if they are compatible with Cortex-A9 or more generally ARMv7-Profile A? I view the data sheet of the 2 RAM. ( https://www.mouser.com/ds/2/12/Alliance%20Memory_%202G%20128Mx16_AS4C128M16D3B-12BCN%20v1-1288833.pdf and www.mouser.com/.../43-46TR16128B-82560BL-276702.pdf ) and search the key word ARM, but nothing found. I search the key word
DDR in the data sheet of the CPU ( https://static.docs.arm.com/100511/0401/arm_cortexa9_trm_100511_0401_10_en.pdf ) but nothing related found.
I think there must be a problem of comptability between an architecture and a RAM. If I want to cooperate a DDR3 RAM with an ARMv1 architecture
CPU, it won't work. Question 2: Why in the data sheet of RAM, the manufacturer doesn't indicate the compatible architecture? Question 3: Why in the data sheet of CPU, the manufacturer doesn't indicate the type of memory(DDR3, DDR4, etc) it supports?
Furthermore, I have 2 questions:
For the ARMv7 Profile A architecture, when translating the virtual address to physical address, a translation table is used. On the page 1324 of the ARMv7 architecture reference manual ( developer.arm.com/.../arm-architecture-reference-manual-armv7-a-and-armv7-r-edition ) , the author describes the organization of the memory on which the Short-descriptor translation table is based:
Sections: Consist of 1MB blocks of memory. Large pages: Consist of 64KB blocks of memory. Small pages: Consist of 4KB blocks of memory.
Question4: Does this way of organization need the support from RAM?
On the page 2 of the data sheet of Alliance memory, it indicates the page size of memory: "1KB page size for X8 / 2KB page size". On the first page of data sheet of ISSI, it indicates "Page size 1KB". But according to the organization of the memory mentioned above, the small page is 4KB. Question5: Can we say that the 2 RAMs doesn't support the architecture ARMv7 Profile A due to that?
Question6: Why the data sheet of the 2 RAMs doesn't indicate the MTBF of the memory?
There is no compatibility between ARM core architecture and DDR(x) RAM, because core exchanges data with DDR(x) RAM via DDR(x)-controller.
For example, you have a SoC (System on Chip) with embedded DDR3 controller and main processor core(s) with architecture of ARM Cortex A9, the main bus infrastructure in the SoC may be one of AMBA buses which connects different controllers of the SoC and main core. So you can use DDR3 RAM of Alliance memory (AS4C128M16D3B-12BCN) with this SoC.
If you want to use some SoC with DDR(x) memory, check the reference manual of the SoC and find out the possibilities of emebedded DDR-controller.
If you want to know more about memory interfaces visit www.jedec.org
Thanks very much for Vanhealsing's answer. It's really helpful! I now have 2 more questions following the answer.
I check the data sheet of a SoC i.MX 6Dual/6Quad. On the page 64, it shows the DDR controller supports the DDR3 compliant to JESD79-3D DDR3 JEDEC standard. 6862.IMX6DQAEC.pdf It supports the bus width 16/32/64 bits.
Then I check the JESD79-3D standard. 7024.JESD79-3D-DDR3 SDRAM Standard.pdfOn the chapter 2.10, it says that the pins of the data bus are DQ. And according to chapter 2, for SDRAM x4, the bus width is 4 (DQ0-DQ3). For SDRAM x8, the bus width is 8(DQ0-DQ7). For SDRAM x16, the bus width is 16(DQL0-DQL7, DQU0-DQU7). Question 7: Does it mean that the maximum data width for the JESD79-3D compliant DDR3 is 16 bits? Question 8: If the answer for question 7 is yes, why the data sheet of the SoC mention that the DDR controller supports DDR3 with bus width 32/64 bits? This kind of DDR3 does not exist.
You're right, according to JESD79-3D (the purpose of this document is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices) bus width may be x4, x8, x16 bits.
Multi-Mode DDR Controller (MMDC) of i.MX6Dual/6Quad processors supports bus width x16, x32 and x64 bits, thereby maximum data bus width for one chip is x16 bits, but MMDC in datasheet specified bus width of x32 bits and x64 bits, I think that is for possibility of usage combined DRAM chips in memory modules.
The DDR3 standard permits DRAM chip capacities of up to 8 gibibits, and up to 4 ranks of 64 bits each for a total maximum of 16 GiB per DDR3 DIMM. (https://en.wikipedia.org/wiki/DDR3_SDRAM)
A memory rank is a set of DRAM chips connected to the same chip select, which are therefore accessed simultaneously. In practice all DRAM chips share all of the other command and control signals, and only the chip select pins for each rank are separate (the data pins are shared across ranks). The term “rank” was created and defined by JEDEC, the memory industry standards group. On a DDR, DDR2, or DDR3 memory module, each rank has a 64 bit wide data bus (72 bit wide on DIMMs that support ECC). The number of physical DRAMs depends on their individual widths. For example, a rank of x8 (8 bit wide) DRAMs would consist of eight physical chips (nine if ECC is supported), but a rank of x4 (4 bit wide) DRAMs would consist of 16 physical chips (18 if ECC is supported). Multiple ranks can coexist on a single DIMM, and modern DIMMs can consist of one rank (single rank), two ranks (dual rank), four ranks (quad rank), or eight ranks (octal rank). See https://en.wikipedia.org/wiki/Memory_rank
Also look at the maximum frequency of Multi-Mode DDR Controller (MMDC) of i.MX6Dual/6Quad processor, 532 MHz is the frequency for DDR3 DRAM from table in datasheet of i.MX 6Dual/6Quad. Check i.MX 6Dual/6Quad Applications Processor Reference Manual to clarify operation of MMDC (and also programming model), chapter 44. Multi Mode DDR Controller (MMDC).
Dear wchgoldbach,
The following application note from NXP has more details on possible DDR configurations with i.MX6:
https://www.nxp.com/docs/en/application-note/AN4397.pdf
As the DDR interface is not the easiest to design, you might also want to start from the reference designs; the i.MX6 SabreSD has a 64b DDR3 for example:
Download
Best regards,
Vincent.