Hi,
I have some assembly for Cortex M4 (Arm 7M Thumb), I want to enable an interrupt that is connected to a push button on an STM32 F407. It works, but for some reason when I enable the set enable register, the clear enable register also gets set ? Is this normal ?
NVIC_BASE EQU 0xE000E100NVIC_ISER0 EQU NVIC_BASESETENA6 EQU 1 << EXTI0_IRQn
EnableButtonINT PROC ;Enables the interrupt for the blue pushbutton LDR r0, =NVIC_ISER0 ;set enable interrupt from EXTI0_IRQn channel LDR r1, =SETENA6 STR r1, [r0] BX LR ENDP
So the code above results in 0x40 on set enable AND clear enable registers !
The reason I ask is that I seem to be getting two interrupts all the time. I've put a debounce on so my flow is
1. Enable interrupts
2. On button interrupt - toggle LED, disable button interrupt (for debounce), use the systick timer to get another interrupt in 200ms
3. On systick interrupt (200 ms after button press), re-enable button interrupt again ie debounce finished
So I'm disabling the button interrupt to prevent repeated button interrupts when user is really only pressing ovce (typical debounce). But I get an interrupt for button on, then when the re-enable occurs I get another one straight away (I've cleared enabled and pending).
Reading the CLEAR ENABLE register returns "1" in the bit positions of the interrupts that are currently enabled, so it sounds like it is behaving as it's supposed to.
From the ARM v7m ARM:
CLRENA, bits[m]
B3 System Address Map B3.4 Nested Vectored Interrupt Controller, NVIC
For register NVIC_ICERn, disables or shows the current enabled state of interrupt (m+(32*n)):
0 On reads, interrupt disabled. On writes, no effect.
1 On reads, interrupt enabled. On writes, disable interrupt.
OK thanks, I have a few more questions on interrupts that you might be able to help with, I think what I'm confused about is why there are 2 registers for active interrupts - set enable and clear enable. I can see them as mutually exclusive, so why not just use a single register ?