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[Cortex-A53] STP instruction stores out of the specified memory

Emmy0

Hi Experts，

     I have a question about "STP" instruction in Cortex-A53.

     STP W6, W6, [SP, #20]  --> after it executes, the memory of [sp, #16] and [sp, #28] are corrupted.

     I don't know why cause it. 

    Can you help to explain the reason? 

    The environment is:

       Before STP executes:

             W6=0x10, SP=0xFFFD36D0, MMU disable, dcache disable, icache enable.

             memory content is:

             [0xFFFD36E0]:  0xFFFD3740 0x00000000 0x00000001 0xFFFD3750

      After STP executes:

             memory content is:

             [0xFFFD36E0]:  0x00000000 0x00000010 0x00000010 0x00100000

      Thanks for your attention!

Best Regards,

Emmy

Parents
  • 0 in reply to MarekBykowski

    Hi MarekBykowski,

         Yes, if Static Memory via AXI4, it works well.

         Unfortunately, my board's Staic Memory is connected AHB, so STP access address is restricted  to 64-bit align. I have worked around in code to avoid "STP" generation. Now it can work.

          Thanks!

    Best Regards,

    Emmy

         

Reply
  • 0 in reply to MarekBykowski

    Hi MarekBykowski,

         Yes, if Static Memory via AXI4, it works well.

         Unfortunately, my board's Staic Memory is connected AHB, so STP access address is restricted  to 64-bit align. I have worked around in code to avoid "STP" generation. Now it can work.

          Thanks!

    Best Regards,

    Emmy

         

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