Hi Experts，
I have a question about "STP" instruction in Cortex-A53.
STP W6, W6, [SP, #20] --> after it executes, the memory of [sp, #16] and [sp, #28] are corrupted.
I don't know why cause it.
Can you help to explain the reason?
The environment is:
Before STP executes:
W6=0x10, SP=0xFFFD36D0, MMU disable, dcache disable, icache enable.
memory content is:
[0xFFFD36E0]: 0xFFFD3740 0x00000000 0x00000001 0xFFFD3750
After STP executes:
[0xFFFD36E0]: 0x00000000 0x00000010 0x00000010 0x00100000
Thanks for your attention!
Best Regards,
Emmy
Hmm, at first sight it looks okey but a couple of things to consider:
- Stack Pointer must be 16 byte aligned but it seem it is in your case- have you tried with w6 and any other register, eg. w7- you have no MMU and hence the memory is not attributed to Memory but to Device. You seem executing code from Devices then which is" Trying to execute code from a region marked as Device, is generally UNPREDICTABLE. Theimplementation might either handle the instruction fetch as if it were to a memory location withthe Normal non-cacheable attribute, or it might take a permission fault. "
so can you try map the region to Memory and re-test?- then if you operate on data from Device then you should not cross the 4K Byte boundary but you seem not in this case.- are you sure nothing else is writing to the adjacent addresses? Another cpu? Are you doing the test from when kernel is up or from within the boot loader?
Hi MarekBykowski,
Thanks for your explaintion!
If I map the region to memory, the issue is disappeared.
But if the region is changed to DDR which is connected AXI bus, under the same environment(no MMU, device type), the code can work well.
Does it be related to the different bus interfaces? AXI is ok, but AHB is wrong.
Emmy0: AXI is ok, AHB is wrong
I don't think AHB is wrong. For example the Static Memory my board is using is connected to the CCN (Cache Coherent Network) through AXI4, not AHB. AHB is less offering and less complex and eg. Coresight uses it.
For the AXI4 behind Static Memory I can run equally well the code being attributed to the Devices and Memory.
Yes, if Static Memory via AXI4, it works well.
Unfortunately, my board's Staic Memory is connected AHB, so STP access address is restricted to 64-bit align. I have worked around in code to avoid "STP" generation. Now it can work.
Thanks!