HI,
Do anyone has a clue on the latency of the MRS CPSR (or APSR) command?
I want to read the flags with no jump (and it is critical).
Thanks
Which processor(s) are you using? If you look at the TRM(s), they sometimes include the cycle information. For example, Cortex-A9 lists MRS as 1 cycle:
infocenter.arm.com/.../ric1447333720404.html