Hello to all,
I am working on Cortex-M4 and in order to implement the load and store instructions, I have chosen the pre and post-index addressing and the memory arrangement is little endian. Therefore during the execution, an observation related to consumed cycles with different pre and post index-addressing has been made. The observation has been represented in the tabular form and true for both load and store instructions and in case of both the mode either pre-index and post addressing mode.
Can anyone provide me an explanation corresponds to such variation in the cycles??
Thanking you,
Kind Regards,
Himanshu
Not sure how to help - If is unclear which instructions you are using and it also depends in the base address values.
There are some information about load/store timing in Cortex-M4 Technical Reference Manual, which might be useful to you.
http://infocenter.arm.com/help/topic/com.arm.doc.100166_0001_00_en/ric1417175925887.html
Unaligned accesses take more time as the access has to be split up.