We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hi experts,
I want to enable monitor debug mode for Cortex-A15 MPCore. I tried modifying DSCR[15] bit but watchpoint event still won't generate exception/abort. Core was in no-debug mode before modifying the DSCR (after power-on). I know I configured the watchpoint registers correctly (tested with debugger, core is halted because it is in a halting debug mode). Is there any pre-condition for enabling this mode (supervisor etc.) or am I using the wrong register or something?
I do this
ldr r1,=0xC5ACCE55 mcr p14,0,r1,c7,c12,6 // // enable monitor mode/disable halt mode // mrc p14,0,r1,c0,c2,2 cmp r0,#0 it NE bicne r1,r1,#0x4000 // disable Halting mode orrs r1,r1,#0x8000 // enable Monitor mode mcr p14,0,r1,c0,c2,2
Thank you. Your code helped a lot. My problem was the debug os lock (DBGOSLAR).