Hi ,
I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core.
Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn't see any Drhit,Dwhit event count register gets updated.
Kindly let me know to Observe the Event Counter register does MMU initialisation required ? or the initialisation sequence is wrong .
MMU enable let's you treat a region as the Cacheable Memory. In other words you cannot have D-Cache without the MMU enabled. I think you may have been observing the correct behavior. With treating a region as a memory allows a number of optimizations (out-of-order execution, merging, speculation, multi-issuing), plus faster memory access if a memory region is Cacheble.