Hi ,
I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core.
Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn't see any Drhit,Dwhit event count register gets updated.
Kindly let me know to Observe the Event Counter register does MMU initialisation required ? or the initialisation sequence is wrong .
Thanks fro the reply Kowski, Will enable MMU and let you know .