TTBR1_EL1 aligment

Hi !

I'm struggling a bit to understand the alignment constraints on the physical address we put in TTBR1_EL1. The ARM ARM v8 doesn't give a precise link in TTBR1_EL1 description to where is alignment is defined. For this post, I'm using a 4k granule everywhere.

From what I understand, bits [x-1,0] must be all 0, for x defined like in table

Table D4-25 Translation table entry addresses when using the 4KB translation granule

For exemple, for a T1SZ of 30, to map 16 GiB of memory, x would be 37 - 30 = 7 (4 x 4k pages)

for a T1SZ of 32, to map 4 GiB of memory, x would be 37 - 32 = 5 (1 x 4k pages)

However in the same table, we see that "BaseAddr[PAMax-1: x]:IA[y:30]:0b000" which would suggest that any look starting at level One needs to be 4K page align.

Could someone clarify the situation, and tell me which constraints I have to fullfuly for the value T1SZ of 30 and 32 ?

Best,

V.