Current Variation due to Functional Unit activation or deactivation

Hi Himanshu,

This will be challenging as the power consumption of each small parts in the processor is insignificant when compared to power consumption of memories, oscillator, clock buffers, etc. Don't forget that for each instruction execution, in parallel you can have instruction fetches, and the power consumption of instruction fetches can be much higher (due to flash memory accesses).

Maybe starting with a simple loop with NOPs

loop:

    NOP

    NOP

    NOP

    ...

    NOP

    B  loop

Observe the power waveform, and then replace one of the instruction in the loop with an ADD instruction to see what is the impact.  Even when NOP is executed, you will still have instruction fetches, and hence exercise one of the bus interface, some parts of the memory system, etc.  You might see a period glitch in the power value when the branch is executed.

If the power pattern doesn't change when you added an ADD instruction, it means the power taken by the ALU in relative to other parts is so small that it is not observable.

regards,

Joseph

Hi Himanshu,

This will be challenging as the power consumption of each small parts in the processor is insignificant when compared to power consumption of memories, oscillator, clock buffers, etc. Don't forget that for each instruction execution, in parallel you can have instruction fetches, and the power consumption of instruction fetches can be much higher (due to flash memory accesses).

Maybe starting with a simple loop with NOPs

loop:

    NOP

    NOP

    NOP

    ...

    NOP

    B  loop

Observe the power waveform, and then replace one of the instruction in the loop with an ADD instruction to see what is the impact.  Even when NOP is executed, you will still have instruction fetches, and hence exercise one of the bus interface, some parts of the memory system, etc.  You might see a period glitch in the power value when the branch is executed.

If the power pattern doesn't change when you added an ADD instruction, it means the power taken by the ALU in relative to other parts is so small that it is not observable.

regards,

Joseph

Hello Mr. Yiu,

Thank you very much for your quick reply. I have tried the sample code, provided by you. From the resultant power pattern, it was difficult to see any difference with 1 ADD instruction in the loop of NOP instruction. But, on trial of more ADD consecutive instruction, there was a significant jump in the power pattern.

What can be the reason, or is it due to the consecutiveness of the ADD instruction only?

Regards,

Himanshu 

In NOP instruction sequence there is no write to register bank so all registers could be clock gated.

When a sequence of ADD instructions are executed, the result of the ADD need to be stored and hence the power used by the register bank would be higher (destination register need to be active every cycle).

regards,

Joseph

Hello Mr. Yiu,

Thank you so much for the explanation. It is really helpful.

Thank you once again,

Regards,

Himanshu