Hello,
Reading the "ARM® Generic Interrupt Controller Architecture version 1.0 Architecture Specification" I read that "For nested interrupts, the order of interrupt completion must be the reverse of the order of interrupt acknowledgment. That is, the order of writes to the ICCEOIR must be the reverse of the order of reads from the ICCIAR.". My first problem is that the specification does not specify the behavior when an not in reverse order write to ICCEOIR happens, nor does it classifies it as UNPREDICTABLE. What would be the problem if I do this?
However, I found that regardless of the order of acknowledgment, when I write ICCEOIR with the id of an active interrupt, that interrupt becomes inactive. I am doing this on a Xilinx Zynq-7000. Should I just expect this on this implementation?
Jose, I noticed on the ZYNQ, that if you write a different id then the last read (or active) nothing happens. So also from my experience, it is save to use the number of the active interrupt to write to EOIR.
Hello Bastian! Thank you once again for your interest in my posts.
From some tests I performed yesterday I agree with your second statement, that is, I believe it is safe to write the id of any active interrupt to EOIR on the ZYNQ. However, I did see something happen when I performed this write - the interrupt became inactive (I got this by reading the ICDABR registers after writing to EOIR) even if another higher priority interrupt was acknowledged after it.