We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hello,
Reading the "ARM® Generic Interrupt Controller Architecture version 1.0 Architecture Specification" I read that "For nested interrupts, the order of interrupt completion must be the reverse of the order of interrupt acknowledgment. That is, the order of writes to the ICCEOIR must be the reverse of the order of reads from the ICCIAR.". My first problem is that the specification does not specify the behavior when an not in reverse order write to ICCEOIR happens, nor does it classifies it as UNPREDICTABLE. What would be the problem if I do this?
However, I found that regardless of the order of acknowledgment, when I write ICCEOIR with the id of an active interrupt, that interrupt becomes inactive. I am doing this on a Xilinx Zynq-7000. Should I just expect this on this implementation?