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Transition to secure monitor flow on ARMv8

Umair Khan

Hi everyone,

Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is running.

In ARM v8 vector table, given on ARMv8-A architecture reference manual page 1800, there are four types of exceptions:

  1. Synchronous
  2. IRQ or vIRQ
  3. FIQ or vFIQ
  4. SError or vSError

As there is no exception with name SMC, I want to ask under which exception type does SMC fall? If I have a baremetal program running on Cortex-A72, what do I need to do if want to write a SMC handler?

Any answers will be highly appreciated,

Thanks

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  • +1

    Exceptions caused by SMC instructions go to the Synchronous exception vector. This makes sense, because the exception is precise and is caused during program execution by an instruction. To know if the exception taken is really an SMC, you have to look at EL3_ESR register, since other things like translation table faults also vector synchronously. The ARMv8 A, Architecture Reference Manual describes how to decode it to figure out if it was indeed an exception caused by the SMC. 

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  • +1

    Exceptions caused by SMC instructions go to the Synchronous exception vector. This makes sense, because the exception is precise and is caused during program execution by an instruction. To know if the exception taken is really an SMC, you have to look at EL3_ESR register, since other things like translation table faults also vector synchronously. The ARMv8 A, Architecture Reference Manual describes how to decode it to figure out if it was indeed an exception caused by the SMC. 

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