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Transition to secure monitor flow on ARMv8

Umair Khan

Hi everyone,

Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is running.

In ARM v8 vector table, given on ARMv8-A architecture reference manual page 1800, there are four types of exceptions:

  1. Synchronous
  2. IRQ or vIRQ
  3. FIQ or vFIQ
  4. SError or vSError

As there is no exception with name SMC, I want to ask under which exception type does SMC fall? If I have a baremetal program running on Cortex-A72, what do I need to do if want to write a SMC handler?

Any answers will be highly appreciated,

Thanks

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    SMC instruction - monitor mode of processor with dedicated banked registers (I am not a prcatical user of ARM Cortex-A ARMv8-A, but if you write the address of your exception handler to vector table and use in your bare metal SMC instruction you may trap to your monitor handler).

    Read more in ARM Cortex-A Series Programmer’s Guide for ARMv8-A, Chapter 4.5 Changing execution state

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  • 0

    SMC instruction - monitor mode of processor with dedicated banked registers (I am not a prcatical user of ARM Cortex-A ARMv8-A, but if you write the address of your exception handler to vector table and use in your bare metal SMC instruction you may trap to your monitor handler).

    Read more in ARM Cortex-A Series Programmer’s Guide for ARMv8-A, Chapter 4.5 Changing execution state

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