Hi,
On Cortex M33 , i am trying to check software interrupt functionality. Below is the CMSIS APIs i used. Note that the CPU is in secure world and secure VTOR is being configured.
Also, ITNS config for this line is set to secure.
NVIC_SetPriorityGrouping(0); NVIC_SetPriority(6, 1); NVIC_EnableIRQ(6); NVIC_SetVector(6, (uint32_t)SwIRQ_Handler); NVIC->STIR = 6;
On ARM FastModel, when i ran this test, i could see that the IRQ gets generated as expected but, i don't see the same on HW.
In HW, IRQ line 6 is tied to 0.
assign cpu_irq_i[6] = 1'b0 ;
Before, i start suspecting the RTL, i wanted to understand , are there any unwritten rules on what interrupt lines can be used for Software interrupt purpose ?
I did find a related link on the community but i couldn't get the answer i was looking for. Hence, reposting the question.
Thanks,
Diwakar
Several things to check on hardware:
- is IPSR == 0 before you start the test?
- is the vector table relocated to SRAM? (if vector table is read-only NVIC_SetVector() won't work).
- Cortex-M33 has a configuration option to disable certain interrupt line.
regards,
Joseph
In the general case, is it an accepted practice to create SW Interrupts by just adding IRQs to the NVIC and assigning the actual IRQ going to the core to 0 in the hardware?Then the only way to trigger these IRQs is by writing NVIC_IPSR<n> or STIR?
It can work, but IRQ is not guarantee to take place immediately (i.e. asynchronous exception). After to write to IPSR / STIR, it could take a number of clock cycles before the interrupt service start. So the code that write to IPSR/STIR will need to poll a software flag to confirm if the ISR is completed.
A better solution is using SVC, which doesn't need such software flag polling as the code that trigger SVC will not continue until SVC has been triggered (i.e. synchronous exception).