Architectures and Processors forum Cortex a15 disable non-blocking cache

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Cortex a15 disable non-blocking cache

pa007 over 9 years ago

Hi, I'm working on ARM Cortex-A15.

Is possible to disable the non-blocking cache behavior?

Is possible to set the in-order execution?

Thanks in advance for the help.

Regards Paolo.

+1 Martin Weidmann over 9 years ago

Curious - why?

But to answer your question, no. While there are some override bits in ACTLR and ACTLR2, there isn't one (AFAIK) to do that.

EDIT: Forgot that there is an issue with apostrophes.
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0 pa007 over 9 years ago in reply to Martin Weidmann

Hi, thanks for the answer.
I'm working on a hypervisor open-source, and I try to implement cache coloring technique for partitioning the cache to different guests. This to ensure time prediction for real-time application. But, with not blocking cache the interference are related to the limited number of MSHR registers (how show in this paper ittc.ku.edu/.../taming-rtas2016-camera.pdf).
Can be possible intercept some interrupt to block the CPU via software to emulate a blocking cache behavior?
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