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armv5TE

kalle over 8 years ago

HI,

I am using an armv5TE (mv78100)I wonder if I need to implement memory barriers in this architecture,(some people say not needed)

reason for my question is that I am facing system total freeze(now and then) and I suspect the system(freebsd) beeing on the idle loop!

Thanks

Top replies

Peter Harris over 8 years ago +1 verified

Architecturally you need to include barriers where ever the architecture says you need to include barriers; anything else is making assumptions about the CPU micro-architecture which may work on some CPUs...

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0 Yasuhiko Koumoto over 8 years ago

Hi qabsou,

do you want the other than the following?
DSB MCR p15,0,<Rd>,c7,c10,4
DMB MCR p15,0,<Rd>,c7,c10,5
If it is true, could you tell what kind of what kind of a memory barrier which you want?
Best regards,
Yasuhiko Koumoto.
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0 Yasuhiko Koumoto over 8 years ago

Hi qabsou,

do you want the other than the following?
DSB MCR p15,0,<Rd>,c7,c10,4
DMB MCR p15,0,<Rd>,c7,c10,5
If it is true, could you tell what kind of what kind of a memory barrier which you want?
Best regards,
Yasuhiko Koumoto.
Cancel
Vote up 0 Vote down

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0 kalle over 8 years ago in reply to Yasuhiko Koumoto

Hi,

Thanks for your attention,

I wonder if I need to implement barriers(I have total freeze problems), I wonder this becauseit is written that ARMv5TE does not have instruction optimization.

I am thinking about the problem when instructions after interrupt enable are executed before

the interrupt enable instruction, this can lead to hang on idle loop.

Thanks

Från: yasuhikokoumoto <community@arm.com>

Till: kalle <tsmoseby@yahoo.no>

Skickat: tisdag, 13 december 2016 3:19

Ämne: Re: - armv5TE

armv5TE

reply from yasuhikokoumoto in kalle - View the full discussionHi qabsou,

do you want the other than the following?DSB MCR p15,0,,c7,c10,5If it is true, could you tell what kind of what kind of a memory barrier which you want? Best regards,Yasuhiko Koumoto.

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