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pre emption of the interrupts in the cortex m3 arm v7

i am a beginner in this subject and i started reading the TRM from the infocenter

one thing confused me

Interrupt grouping    in this link it is written as

"Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler,

If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first."

and in this link ARM Exception entry and return

there is one more contradictory statement for the above statement (i feel)

"When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See Interrupt priority grouping for more information about preemption by an interrupt. "

in the first link why did they write like that if its PRIGROUP is 011 and if one interrupt sub group number is 2 and it's handler is currently running mean while if the interrupt with subgroup 1 of same priority group  occurs then why doesnot it preempt the 2 and go to 1's handler?  why does it preempt only when multiple interrupts of same group priority are  present ?

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  • Hi srikar ,

    I am afraid you have some misunderstandings.

    The second line dones not at all refer to the pre-emption of interrupts.

    The several pending interrupts of the same priority (and the same subpriprity) will be served sequentially (without any pre-emption) according to the interrupt number.

    If the number of pending interrupts was one, the service order was already determined (in only one order) among the same priority group.

    Best regards,

    Yasuhiko Koumoto.