hi :
I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*).
however, I can not find any clue about flushing L2 cache to DRAM(if without L3).
and I saw some points that L2 flushing was not needed.
for ARMv8, how can OS control the L2 cache for enable/disable/flush(maybe?) ?
for ARM v7, there was a L2 controller(pl310) to control L2.
hi Ash:
thanks a lot !
your explanation is so perfect for me !
as your said, I check the trust zone firmware, I can find:
functions cortex_a53_core_pwr_dwn & cortex_a53_cluster_pwr_dwn include more details that I'm interested in.
first turn off cache , then flush L1 cache, and flush L2 cache(if cluster power down).