is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?

hi :

I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*).

however, I can not find any clue about flushing L2 cache to DRAM(if without L3). 

and I saw some points that L2 flushing was not needed.

for ARMv8,  how can OS  control the L2 cache for enable/disable/flush(maybe?) ?

for ARM v7,  there was a L2 controller(pl310) to control L2.