Hi.
I am writing back regarding MPU usage. I implemented it into the software in next ways (note, that program is quite simple - only privileged mode, no RTOS):
1. I enabled background region, thus all addressable memory is fully accessible, unless there is no any other region defined above certain address range.
2. Defined Flash as READ ONLY (except few pages at the end where we store some tables, etc.).
3. Defined SRAM as fully accessible (R/W), but with XN (execute never) property enabled.
4. Defined CCM RAM (all code which is executing run time is stored in CCM, so program in while(1) loop is executed from there, not from flash -> gain in speed) as READ ONLY.
5. Defined the lowest 256 B of stack as non accessible. I do that by first reading the top of the heap (via exported __heap_limit from startup file), then mask out the least significant byte from that address (because of alignment requirements between MPU region size and start address), incremented it by 256 B (0x100) to leave heap unaffected and set this as start address for MPU region.
Now, I would like to ask if there is any other (more direct way) to define start address of MPU region for stack overflow detection?
Second, I would like to ask, if you suggest also any other MPU usage for such system?
And finally, a question regarding "bufferable" property of MPU region. Do I have to (or at least is it better to) enable this property for ROM, SRAM and CCM RAM, if I want to have max performance? Or does it not effect anything?
Best regard.
Hi matic,
I can answer only the last question.
Interpretation of the bufferable attribute is responsible to the peripheral devices which will receive the transaction.
Also the bufferable is usually used for the buffering of the write data.
I think there would not be useful to add the bufferable attribute to the read only memory.
Best regards,
Yasuhiko Koumoto.
Thank you.
Then bufferable attribute is useful only when WRITE operation is executed. If I understand correctly, attributes like cacheable and shareable also have nothing to do with a single processor MCU without cache. Only XN do have its role.
Thank you