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Cortex A9 single core

Vincent Siles

From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions:

SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated

as Non-Cacheable:

• all pages marked as Write-Through are treated as Non-Cacheable

• if ACTLR.SMP=0, all pages marked as Shared are treated as Non-Cacheable.

I am only running on a single core, and I want to enable L1 and L2 caches without enabling the SCU (I have issues with that at the moment).

I tried to set ACTLR.SMP to 1 with the SCU disabled without any success so far (I get memory corruption), so how should I set my MMU to get L1 and L2 caches on ?

I think I need to map my pages with the S bit set to 0, is that correct ?

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