In the PL310 TRM, the definition of the CACHE_ID register define the RTL release as the lower bits of the register.
To translate this RTL to a revision information, it is stated that
"RTL release 0x9 denotes r3p3 code of the cache controller. See the Release Note for the
value of these bits for other releases."
Where can I find these release notes to understand the value read from this register ?
Best,
Vincent
Hi !
As you guessed, the context was to be sure which errata I should consider in my code. I am using the document you linked (and the imx6 errata from NXP), which all refers to revision number as rXpX, but they don't use the RTL release number.
For example in the document you linked, page 14, errata 727914, we can read:
Fault Status: Present in: r3p0. Fixed in r3p1. Unchanged in this document.
I can't find any mention of the RTL version. I found such information in the code source of Linux, but I'd like to have the official source for this translation to be sure of what I'm doing.
V.
Hi vsiles,
It is a little obscure, agreed. The best way is to look at the errata and then cross-check that errata release note vs. the cache ID register for that release (each document dictates which RTL release number corresponds to -- in the documentation for the Cache ID register itself). You will note that r3p1 and r3p2 skip a version (0x6 -> 0x8). To reference an errata document, 742884 specifically mentions a r3p1-50rel0 release, and you can pretty well infer that it's RTL release 0x7.
AMBA Level 2 Cache Controller (L2C-310) Technical Reference Manual: 3.3.1. Cache ID Register (r3p1)
CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual: 3.3.1. Cache ID Register (r3p2)
So you can always differentiate them in software..
Ta,
Matt
Ok, I understand now. Thank you for the detailed answer !