Hi everyone ,
I'm currently using a Cortex-A9 processor (NXP Freescale i.MX6S).
My project is to develop a simple OS, but I met a problem:
When I am trying to control some peripherals (such as UART and GPIO) directly under ARM USER MODE, the program stopped and jumped into some other exceptional handlers.
However, if I control these peripherals under ARM SYSTEM MODE, everything is fine.
I know that there are 7 ARM modes, USER mode is the non-privilege mode and the others are privilege modes. USER mode is redistricted in accessing some resources, but I didn't find out any document explain these restrictions explicitly.
Could you give me some advises? Very Appreciate it !!!
There are restrictions in terms of control register accesses, but there's no specific restriction in terms of memory mapped peripheral access; it all depends on the permissions you have set in your page tables.
The fault address and fault status registers should be able to give you a good clue what is going wrong.
More info here: ARM Information Center
Cheers, Pete
Hello Pete,
could you give us the concrete list of the privileged instructions?
I think MCR/MRC and MSR/MRS would be the privileged instructions.
However, I don't know whether the other privileged instructions exist.
Thank you and best regards,
Yasuhiko Koumoto.
In the case of MSR/MRS and MCR/MRC, it's not the instructions that are privileged - but what you are accessing. That is, User mode/EL0 can use these instructions as long the accessed register permits it.
For example, PMSELR (PMU Counter Selection Register) can be accessed from User mode/EL0. And you would do this via MCR/MRC (ARMv7-A/AArch32) or MSR/MRS (ARMv8-A AArch64).
In terms of "privileged" instructions, there are some. For example, SMC and HVC both require privileged access. As do some many cache and TLB maintenance operations.
Although as Peter says, here it's to do with memory mapped peripherals. So it will be down to the page tables.
Hello Martin,
thank you for your response.
I understood well.
Best regards,
helpful
Thank you very much Peter and Martin!
So I should look into the MMU configuration for page tables, am I right?