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Differences between Privilege Modes and Non-Privilege Mode ?

Rui

Hi everyone ,

I'm currently using a Cortex-A9 processor (NXP Freescale i.MX6S).

My project is to develop a simple OS, but I met a problem:   

When I am trying to control some peripherals (such as UART and GPIO) directly under ARM USER MODE, the program stopped and jumped into some other exceptional handlers.

However, if I control these peripherals under ARM SYSTEM MODE, everything is fine.

I know that there are 7 ARM modes, USER mode is the non-privilege mode and the others are privilege modes. USER mode is redistricted in accessing some resources, but I didn't find out any document explain these restrictions explicitly.

Could you give me some advises? Very Appreciate it !!!

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  • 0 Arm Employee Badge in reply to Yasuhiko Koumoto

    In the case of MSR/MRS and MCR/MRC, it's not the instructions that are privileged - but what you are accessing.  That is, User mode/EL0 can use these instructions as long the accessed register permits it.

    For example, PMSELR (PMU Counter Selection Register) can be accessed from User mode/EL0.  And you would do this via MCR/MRC (ARMv7-A/AArch32) or MSR/MRS (ARMv8-A AArch64).

    In terms of "privileged" instructions, there are some.  For example, SMC and HVC both require privileged access.  As do some many cache and TLB maintenance operations.

    Although as Peter says, here it's to do with memory mapped peripherals.  So it will be down to the page tables.

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  • 0 Arm Employee Badge in reply to Yasuhiko Koumoto

    In the case of MSR/MRS and MCR/MRC, it's not the instructions that are privileged - but what you are accessing.  That is, User mode/EL0 can use these instructions as long the accessed register permits it.

    For example, PMSELR (PMU Counter Selection Register) can be accessed from User mode/EL0.  And you would do this via MCR/MRC (ARMv7-A/AArch32) or MSR/MRS (ARMv8-A AArch64).

    In terms of "privileged" instructions, there are some.  For example, SMC and HVC both require privileged access.  As do some many cache and TLB maintenance operations.

    Although as Peter says, here it's to do with memory mapped peripherals.  So it will be down to the page tables.

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