This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

ARM CM4 FPU execption

I am looking for FPU exception generation code. If some one share, or suggest some document for the same.

Regards

Anuj

Parents
  • Hi Anuj,


    there would be several cases to produce the floating point execeptions.
    I would show the below examples.

    FPExc_InvalidOp
         +infinity + (–infinity)
    FPExc_DivideByZero
         normalized number / zero
    FPExc_Overflow
         maximum normalized number + 1
    FPExc_Underflow
         minumum normalized number - 1
    FPExc_Inexact
         maximum normalized number + minumum normalized number
    FPExc_InputDenorm
         operand is denormalized number

    In Cortex-M4 case, the enable bits seem not to be implemented.
    So, you can only see the accumulated exception results in FPSCR.

    Best regards,

    Yasuhiko Koumoto.

Reply
  • Hi Anuj,


    there would be several cases to produce the floating point execeptions.
    I would show the below examples.

    FPExc_InvalidOp
         +infinity + (–infinity)
    FPExc_DivideByZero
         normalized number / zero
    FPExc_Overflow
         maximum normalized number + 1
    FPExc_Underflow
         minumum normalized number - 1
    FPExc_Inexact
         maximum normalized number + minumum normalized number
    FPExc_InputDenorm
         operand is denormalized number

    In Cortex-M4 case, the enable bits seem not to be implemented.
    So, you can only see the accumulated exception results in FPSCR.

    Best regards,

    Yasuhiko Koumoto.

Children