We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Dear sirs,
From the specification from ARM architecture, DMB needs to make the load and store operation before DMB instruction have an explicit ordering. However, the description of DMB is a loop which is very difficult to understand.
DMB only cares about memory access ordering while DSB requires all memory access before it are finished. So what is the boundary of DMB in memory access? When can I know that DMB can finish?
In single core processor, DMB can finish when all memory access are sent to L1 memory system, is it right?
In multiple core processor, DMB can finish when all memory access are sent to L2 memory system, is it right?
While DSB is very easy to understand, DSB needs all load and store operation are finished. So all bus operations are finished and all buffer are empty, is it right?
It seems the difference of DMB and DSB in multi-core is very little.
Please correct me when there is any mistake.
Thanks.
Cray
Message was edited by: cray
Hi Yasuhikokoumoto,
This link can partially answer my question, but it doesn't explain the difference between DMB and DSB. It only describes the behavior of DSB.
DMB expresses a logical condition that must be met by store accesses before and after it. It does not stop instructions after it being executed - it just tells the cache about the requirement and it is up to that and things outside of that to ensure the condition is met. The DSB instruction is the one to use when accesses that may not follow the standard memory access rules are involved for instance when changing user context. It is very desirable to try and avoid clearing the cache or doing too many memory accesses when a DMB is done so how to implement the condition is an important hardware design decision. The actual implementation can be quite tricky.
Hi Daith
Thanks for your clarification. It helps me much.
cray