I am looking for ECC insertion method (any instruction) on any address with ARM Cortex M4.

Hello Yasuhiko Koumoto,

Thanks for your answer.

As of now I am looking for SRAM validation. SRAM supports ECC feature, Now I want to insert ECC error on address space of sram.

If there is any instruction or way to insert ECC error on some address(For testing purpose) then it will be very helpful.

Best Regards,

Anuj

Hello Yasuhiko Koumoto,

Thanks for your answer.

As of now I am looking for SRAM validation. SRAM supports ECC feature, Now I want to insert ECC error on address space of sram.

If there is any instruction or way to insert ECC error on some address(For testing purpose) then it will be very helpful.

Best Regards,

Anuj

Hello Anuj,

do you want to validate by RTL or Gate Level?

Or a real chip level?

If you are saying about a real chip validation, it is impossible to insert ECC error unless the chip has such the feature as hardware.

Best regards,

Yasuhiko Koumoto.

Hello Yasuhiko Koumoto,

Thanks for your reply.

I am looking for chip level, when there is no method available for ecc insertion.

I have one idea:

Don' initialize one section of SRAM and try to read that area, might be we can hit single bit or double bit ecc error at some random location in uninitialized area.

But this will not give proper control.

Best Regards,

Anuj