The TRM for the a-57 states that PMCEID0_EL0: Defines which common architectural and common micro-architectural feature events are implemented. PMCEID1_EL0 is a continuation of this list. If a bit position is a "1" that means the even is implemented. Yet there are far more than 32 events listed in the TRM and I've had success setting the PMU to watch for events beyond the events shown to be implemented by PMCEID0_EL0. For instance reading PMCEID1_EL1 returns 0 but configuring counters to count memory reads or writes returns seemingly correct information. So if the event counters are able to be configured to values outside of PMCEID0_EL0 what is its purpose? Or am I misunderstanding its function and this dictates the availability of another tool outside of the 6 PMU configurable counters?
OK, I understood what you said.
Because I have no Cortex-A57 environment, I cannot comment to the undocumented behavior.
I am sorry for not helping you.
Best regards,
Yasuhiko Koumoto.