The TRM for the a-57 states that PMCEID0_EL0: Defines which common architectural and common micro-architectural feature events are implemented. PMCEID1_EL0 is a continuation of this list. If a bit position is a "1" that means the even is implemented. Yet there are far more than 32 events listed in the TRM and I've had success setting the PMU to watch for events beyond the events shown to be implemented by PMCEID0_EL0. For instance reading PMCEID1_EL1 returns 0 but configuring counters to count memory reads or writes returns seemingly correct information. So if the event counters are able to be configured to values outside of PMCEID0_EL0 what is its purpose? Or am I misunderstanding its function and this dictates the availability of another tool outside of the 6 PMU configurable counters?
Hi,
because PMCEID1_EL1 does not exist, I think you say about PMCEID1_EL0.
According to Cortex-A57 TRM, the initial (or permanent) value is 0x00000000.
Also, the initial (or permanent) value is 0x7FFF0F3F.
According to the TRM, only 26 events are available.
What is the back ground of the statement "more than 32 events listed in the TRM"?
Best regards,
Yasuhiko Koumoto.
Here is a link to the TRM that references all 83 events that are able to be observed: ARM Information Center . Yes I did mean PMCEID1_EL0 it returns 0x00000000 and PMCEDI0_EL0 returns 0x7FFF0F3F. Even though event 0x66 and even 0x67 aren't listed as being implemented they return valid results in the counters configured. Thanks for taking the time to explain this to me.
OK, I understood what you said.
Because I have no Cortex-A57 environment, I cannot comment to the undocumented behavior.
I am sorry for not helping you.