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How to configure L2 cache in Cortex-A7

Cherma Rajan

Hi all,

I am working on OrangePi board. The board configuration is,

  • Quad-Core ARM Cortex-A7, 1.6 GHz
  • 32 KB L1 I-Cache and 32 KB L1 D-Cache per core
  • 512 KB L2-Cache

I have few queries related to Cache memory,

  1. How to disable L2 cache of Cortex-A7 in the board?
  2. How to configure L2 cache size of Cortex-A7? (ARM TRM says L2 cache is configurable)

Thanks in advance.