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How to configure L2 cache in Cortex-A7

Cherma Rajan

Hi all,

I am working on OrangePi board. The board configuration is,

  • Quad-Core ARM Cortex-A7, 1.6 GHz
  • 32 KB L1 I-Cache and 32 KB L1 D-Cache per core
  • 512 KB L2-Cache

I have few queries related to Cache memory,

  1. How to disable L2 cache of Cortex-A7 in the board?
  2. How to configure L2 cache size of Cortex-A7? (ARM TRM says L2 cache is configurable)

Thanks in advance.

  • +1

    I have few queries related to Cache memory,

    1. How to disable L2 cache of Cortex-A7 in the board?

    There is only one way on the Cortex-A7 -- and it is to not enable the cache enable bit at all (SCTLR.C bit) which will prevent any allocation into the caches at all architectural levels (L1 and L2). However if it was previously enabled, there may still be valid lines in the cache (it just won't add new ones) and even while disabled, it may still 'naturally' evict those lines, showing some evidence of activity caused by the caches. After disabling the caches you may want to invalidate them.

    If you want to not use the L2 cache, but keep using the L1 cache, that's somewhat difficult. The L2 in the Cortex-A7 is "tightly coupled" in the sense that it is always present, and always going to be used.

    1. How to configure L2 cache size of Cortex-A7? (ARM TRM says L2 cache is configurable)

    You don't -- whoever designed the SoC on the OrangePi board configured the size of the cache for you. All you can do is turn it on and off with the rest of the cache subsystem.

    Ta,

    Matt