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INVPC Hard fault exception error

DrWhom DrWhom
Note: This was originally posted on 16th July 2009 at http://forums.arm.com

Using and Arm Cortex M3, the application that is running sometimes will generate a hard fault and deciphering the CFSR register tells me that the following user fault is triggerred.

From the Cortex manual:INVPC - Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid
value. The return PC points to the instruction that tried to set the PC.

Not sure where to proceed as the PC is pointing to the line in the exception handler. I am trying to figure out the instruction that triggerred the hard fault. Anybody have any suggestions?
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    Note: This was originally posted on 16th July 2009 at http://forums.arm.com

    There are a number of possible reasons for this fault.  For example

    1) Invalid value in EXC_RETURN number during exception return.
    For example,
    "¢ Return to thread with EXC_RETURN = 0xFFFFFFF1
    "¢ Return to handler with EXC_RETURN = 0xFFFFFFF9
    To investigate the problem, the current LR value provides the value of LR at the failing exception return.

    2) Invalid exception active status. For example:
    "¢ Exception return with exception active bit for the current exception already cleared. Possibly caused by use of VECTCLRACTIVE, or clearing of exception active status in NVIC SHCSR.
    "¢ Exception return to thread with one (or more) exception active bit still active.

    3) Stack corruption causing the stacked IPSR to be incorrect.
    For INVPC fault, the Stacked PC shows the point where the faulting exception interrupted the main / preempted program. To investigate the cause of the problem, it is best to use exception trace feature in ITM.

    4) ICI/IT bit invalid for current instruction.  This can happen when a multiple-load/store instruction gets interrupted and, during the interrupt handler, the stacked PC is modified.  When the interrupt return takes place, the non-zero ICI bit is applied to an instruction that do not use ICI bits.  The same problem can also happen due to corruption of stacked PSR.

    regards,
    Joseph
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  • 0
    Note: This was originally posted on 16th July 2009 at http://forums.arm.com

    There are a number of possible reasons for this fault.  For example

    1) Invalid value in EXC_RETURN number during exception return.
    For example,
    "¢ Return to thread with EXC_RETURN = 0xFFFFFFF1
    "¢ Return to handler with EXC_RETURN = 0xFFFFFFF9
    To investigate the problem, the current LR value provides the value of LR at the failing exception return.

    2) Invalid exception active status. For example:
    "¢ Exception return with exception active bit for the current exception already cleared. Possibly caused by use of VECTCLRACTIVE, or clearing of exception active status in NVIC SHCSR.
    "¢ Exception return to thread with one (or more) exception active bit still active.

    3) Stack corruption causing the stacked IPSR to be incorrect.
    For INVPC fault, the Stacked PC shows the point where the faulting exception interrupted the main / preempted program. To investigate the cause of the problem, it is best to use exception trace feature in ITM.

    4) ICI/IT bit invalid for current instruction.  This can happen when a multiple-load/store instruction gets interrupted and, during the interrupt handler, the stacked PC is modified.  When the interrupt return takes place, the non-zero ICI bit is applied to an instruction that do not use ICI bits.  The same problem can also happen due to corruption of stacked PSR.

    regards,
    Joseph
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