Is there an intrinsic limit to the width of the bit banding for peripherals for the
Cortex M3?
EFM32 Giant Gecko seems to have a limit of eight bits - bits 8 to 31 does not seem to work.
Is this normal?
Hi,
As I understand it, the hardware is kind of magic - there exists, for a register,another region in ram, where the bits in the register are represented as thebit 0 in consecutive 32 bit words.
So if the register lives at say addy1, there exists an array of 32 bit ints at anotheraddress, say addy2, where the relationship between addy1 and addy2 is fixed by the relationship between the Register region base address (addy1 is somewhere in this region) and the bit band alias region base address (addy2 is in this region)
Bit 0 of the first register in the register region has a representation at bit 0 of the first 32 bitword in the bit band alias region.
Then Bit 1 of the first of the registers has a representation at bit 0 of the second 32 bit word in the bit alias region.
and so on - there is a 32 bit word in the bit alias region for every bit in the register region, allfollowing consecutively on one another - four bytes for every bit, but only the first bit means anything.
And the magic is that when you write or read to or from any of these bit 0's in the alias region, then you actually access the corresponding bit in the register region. (Or in the ram - there issuch a word for each of the bits in the ram too, at a different place)
so setting tim0_of_ie =1; is writing to the bit band alias of the OF bit in the IEN register, bit 0 of the IEN register, that is bit 0 of the alias word at &tim0_of_ie
tim0_icbof0_ie = 1; similarly, this writes a one to the alias word that is supposed to be representing the bit 8 of the IEN register - but at a different place, namely at &tim0_icbof0_ie
and the relationship between the alias addresses is that tim_icbof0_ie lives at 8 * 4 = 32 bytes higher inthe memory than the place where tim0_of_ie lives, because OF is at bit 0 and ICBOF0 is at bit 8.
So no the accesses are not the same, they are at very different memory positions in the alias area, even though both of the bits in the register live at position zero of their respective bytes.
Does that answer your question, or have I misunderstood?
- Hendrik
From: yasuhikokoumoto <community@arm.com>
To: H van Rooyen <shapeshifter_100@yahoo.com>
Sent: Friday, March 4, 2016 9:19 AM
Subject: Re: - Cortex M3 peripheral Bit Banding limit?
Cortex M3 peripheral Bit Banding limit?
reply from yasuhikokoumoto in ARM Processors - View the full discussionHi,
can I ask one more question?
If we assume the bit banding access to the peripheral registers is 8 bit size, I imagine bothtim0_of_ie = 1;andtim0_icbof0_ie = 1;would be the same.I am afraid the APB cannot distinguish 8 bit accesses (or it would be interpreted as 32 bit).
That is, the "tim0_icbof0_ie = 1" would set IER[0].
What is the fact?
Because I have no Gecko MCUs, I cannot do the experiment.
Although I have Kinetis MCU, almost all bits in the peripheral registers are located in the lower 8 bit range.
Best regards,
Yasuhiko Koumoto.
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Hello Hendrik,
probably it would not be my answer.
The physical address of TIMER0->IEN is 0x4001000c.
I guess as the following.
"tim0_of_ie=1" will modify the bit 0 of the content of 0x4001000c.
"tim0_icbof0_ie=1" will modify the bit 0 of the content of 0x4001000d (this is not a typo).
However, because the TIMER0 and the other peripherals exist under APB via AHB-to-APB bridge in the Giant Gecko MCU, both accesses for 0x4001000c and 0x4001000d are interpreted as the access for 0x4001000c.
Therefore I predict both "tim0_of_ie=1" and "tim0_icbof0_ie=1" would set the bit 0 of 0x4001000c.
I would like to know whether it would be correct or not.
Thank you and best regards,
Hi Yasuhiko San,
Yes the bit 8 is supposed to affect the bit 0 at address 0x4001000d, via the bit bandingalias mechanism.
I have just tested it using a char access, and it does not write to bit 0 at address 0x40001000c,nor to bit 0 at 0x40001000d - just does nothing that I can see.
So its a more complex issue.
It turns out that the EFM32 micros need 32 bit accesses for the peripheral bit band alias area, else one gets the behaviour I have described.
If I use 32 bit accesses, then everything works as expected, and I can access the higher order bits individually via the bit banding access mechanism.
It is strange, because in the case of the ram bit banding, the char accesses work for all the bits.
So in a sense my immediate problem is solved - all I have to do is to use int instead of char, and everything starts working as expected.
Thanks for your interest anyway.
Sent: Friday, March 4, 2016 11:25 PM
reply from yasuhikokoumoto in ARM Processors - View the full discussionHello Hendrik, probably it would not be my answer.The physical address of TIMER0->IEN is 0x4001000c.I guess as the following."tim0_of_ie=1" will modify the bit 0 of the content of 0x4001000c."tim0_icbof0_ie=1" will modify the bit 0 of the content of 0x4001000d (this is not a typo).However, because the TIMER0 and the other peripherals exist under APB via AHB-to-APB bridge in the Giant Gecko MCU, both accesses for 0x4001000c and 0x4001000d are interpreted as the access for 0x4001000c.Therefore I predict both "tim0_of_ie=1" and "tim0_icbof0_ie=1" would set the bit 0 of 0x4001000c.I would like to know whether it would be correct or not. Thank you and best regards,Yasuhiko Koumoto.
Hi Hendrik,
thank you for your summary.
Can I confirm a thing?
Do you say
#define tim0_icbof0_ie *((volatile uint32_t*)(BITBAND_PERI(TIMER0->IEN,8)))
can access the bit 8 of the IEN register?
Otherwise, you can simply say you gave up the bit banding to access such bits as bigger than the bit 8 position?
Yasuhio Koumoto.
here is the macro I use:
#define tim0_icbof0_ie *((volatile unsigned int *)(BITBAND_PERI(TIMER0->IEN,8)))
then, in the setup routine for the interrupt I use the bit banding to access the bit:
tim0_icbof0_ie = 1; // capture buffer overflow interrupt set
And it just works, setting bit 8 of the IEN register of TIMER0 - if you change the int in the macro to a char, it does not work.
So yes using uint32_t will also work.
It makes no sense, it has to be peculiar to the EFM32 register bit band implementation, as char accesseswork for the bit banding in the ram.
shrug
Sent: Saturday, March 5, 2016 3:57 PM
reply from yasuhikokoumoto in ARM Processors - View the full discussionHi Hendrik,thank you for your summary.Can I confirm a thing?Do you say#define tim0_icbof0_ie ((volatile uint32_t)(BITBAND_PERI(TIMER0->IEN,8)))can access the bit 8 of the IEN register?Otherwise, you can simply say you gave up the bit banding to access such bits as bigger than the bit 8 position?Thank you and best regards,Yasuhio Koumoto.
I don't think so.It should be thought differently to access peripheral registers and SRAM.Commonly speaking, the peripheral registers are assumed by what access size can be accessible.In EFM32 case, the access size for the peripheral registers seems to have to be 32bit width.
This would not be a restriction but a specification.Therefore, the accesses for the bit band alias area of the peripheral registers would be 32bit width. That is, LDR/STR should be used.From the discussion till now, I have become a confident that actual register or SRAM area access size (i.e. 8. 16, 32bit) would be the same as the size for the bit band alias area.
For example,
case 1:#define tim0_icbof0_ie *((volatile unsigned int *)(BITBAND_PERI(TIMER0->IEN,8)))tim0_icbof0_ie = 1will act as 1) LDR r0,[r1] // r1 contains TIMER0->IER address2) ORR r0,r0,#(1<<8)3) STR r0,[r1]and case 2:#define tim0_icbof0_ie *((volatile unsigned short *)(BITBAND_PERI(TIMER0->IEN,8)))tim0_icbof0_ie = 1will act as 1) LDRH r0,[r1] // r1 contains TIMER0->IER address2) ORR r0,r0,#(1<<8)3) STRH r0,[r1]and case 3:#define tim0_icbof0_ie *((volatile unsigned char *)(BITBAND_PERI(TIMER0->IEN,8)))tim0_icbof0_ie = 1will act as 1) LDRB r0,[r1] // r1 contains TIMER0->IER address2) ORR r0,r0,#(1<<8)3) STRB r0,[r1]
I think I have completely understood the phenomenon.Also I have no further question.
Best regards,Yasuhiko Koumoto.