Is there an intrinsic limit to the width of the bit banding for peripherals for the
Cortex M3?
EFM32 Giant Gecko seems to have a limit of eight bits - bits 8 to 31 does not seem to work.
Is this normal?
Hi Yasuhiko San,
Yes the bit 8 is supposed to affect the bit 0 at address 0x4001000d, via the bit bandingalias mechanism.
I have just tested it using a char access, and it does not write to bit 0 at address 0x40001000c,nor to bit 0 at 0x40001000d - just does nothing that I can see.
So its a more complex issue.
It turns out that the EFM32 micros need 32 bit accesses for the peripheral bit band alias area, else one gets the behaviour I have described.
If I use 32 bit accesses, then everything works as expected, and I can access the higher order bits individually via the bit banding access mechanism.
It is strange, because in the case of the ram bit banding, the char accesses work for all the bits.
So in a sense my immediate problem is solved - all I have to do is to use int instead of char, and everything starts working as expected.
Thanks for your interest anyway.
- Hendrik
From: yasuhikokoumoto <community@arm.com>
To: H van Rooyen <shapeshifter_100@yahoo.com>
Sent: Friday, March 4, 2016 11:25 PM
Subject: Re: - Cortex M3 peripheral Bit Banding limit?
Cortex M3 peripheral Bit Banding limit?
reply from yasuhikokoumoto in ARM Processors - View the full discussionHello Hendrik, probably it would not be my answer.The physical address of TIMER0->IEN is 0x4001000c.I guess as the following."tim0_of_ie=1" will modify the bit 0 of the content of 0x4001000c."tim0_icbof0_ie=1" will modify the bit 0 of the content of 0x4001000d (this is not a typo).However, because the TIMER0 and the other peripherals exist under APB via AHB-to-APB bridge in the Giant Gecko MCU, both accesses for 0x4001000c and 0x4001000d are interpreted as the access for 0x4001000c.Therefore I predict both "tim0_of_ie=1" and "tim0_icbof0_ie=1" would set the bit 0 of 0x4001000c.I would like to know whether it would be correct or not. Thank you and best regards,Yasuhiko Koumoto.
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Hi Hendrik,
thank you for your summary.
Can I confirm a thing?
Do you say
#define tim0_icbof0_ie *((volatile uint32_t*)(BITBAND_PERI(TIMER0->IEN,8)))
can access the bit 8 of the IEN register?
Otherwise, you can simply say you gave up the bit banding to access such bits as bigger than the bit 8 position?
Thank you and best regards,
Yasuhio Koumoto.
Hi,
here is the macro I use:
#define tim0_icbof0_ie *((volatile unsigned int *)(BITBAND_PERI(TIMER0->IEN,8)))
then, in the setup routine for the interrupt I use the bit banding to access the bit:
tim0_icbof0_ie = 1; // capture buffer overflow interrupt set
And it just works, setting bit 8 of the IEN register of TIMER0 - if you change the int in the macro to a char, it does not work.
So yes using uint32_t will also work.
It makes no sense, it has to be peculiar to the EFM32 register bit band implementation, as char accesseswork for the bit banding in the ram.
shrug
Sent: Saturday, March 5, 2016 3:57 PM
reply from yasuhikokoumoto in ARM Processors - View the full discussionHi Hendrik,thank you for your summary.Can I confirm a thing?Do you say#define tim0_icbof0_ie ((volatile uint32_t)(BITBAND_PERI(TIMER0->IEN,8)))can access the bit 8 of the IEN register?Otherwise, you can simply say you gave up the bit banding to access such bits as bigger than the bit 8 position?Thank you and best regards,Yasuhio Koumoto.
Hello Hendrik,
I don't think so.It should be thought differently to access peripheral registers and SRAM.Commonly speaking, the peripheral registers are assumed by what access size can be accessible.In EFM32 case, the access size for the peripheral registers seems to have to be 32bit width.
This would not be a restriction but a specification.Therefore, the accesses for the bit band alias area of the peripheral registers would be 32bit width. That is, LDR/STR should be used.From the discussion till now, I have become a confident that actual register or SRAM area access size (i.e. 8. 16, 32bit) would be the same as the size for the bit band alias area.
For example,
case 1:#define tim0_icbof0_ie *((volatile unsigned int *)(BITBAND_PERI(TIMER0->IEN,8)))tim0_icbof0_ie = 1will act as 1) LDR r0,[r1] // r1 contains TIMER0->IER address2) ORR r0,r0,#(1<<8)3) STR r0,[r1]and case 2:#define tim0_icbof0_ie *((volatile unsigned short *)(BITBAND_PERI(TIMER0->IEN,8)))tim0_icbof0_ie = 1will act as 1) LDRH r0,[r1] // r1 contains TIMER0->IER address2) ORR r0,r0,#(1<<8)3) STRH r0,[r1]and case 3:#define tim0_icbof0_ie *((volatile unsigned char *)(BITBAND_PERI(TIMER0->IEN,8)))tim0_icbof0_ie = 1will act as 1) LDRB r0,[r1] // r1 contains TIMER0->IER address2) ORR r0,r0,#(1<<8)3) STRB r0,[r1]
I think I have completely understood the phenomenon.Also I have no further question.
Best regards,Yasuhiko Koumoto.