For eg. the A15 on the Samsung Exynos 5422 has around 19 DVFS levels which varies frequencies from 200MHz to 2GHz.
What does ARM guarantee when you sell a design ? The highest and lowest frequencies/voltage levels at which the design works for a particular technology ? And everything in between is left to the implementation ? You don't even suggest any guidelines ?
Basically, the motivation for my question came from observing two designs.
1) The ARM A9 on the OMAP4430 from TI based on 45nm. This one has 4 DVFS levels.
2) The ARM A15 on the Samsung Exynos 5422 based on 28nm. This one has 19 DVFS levels.
We do of course provide guidance on what we expect, but on the whole it's entirely down to the silicon implementation, as different partners will want to achieve different things for their designs to suit their target market.
Even on any one process node it is possible to move the eventual performance/power/area characteristics around significantly depending what a given SoC wants to achieve (lower static power, lower dynamic power, smaller area, faster frequency, etc) just by altering the choices of transistors used.
Cheers, Pete