For eg. the A15 on the Samsung Exynos 5422 has around 19 DVFS levels which varies frequencies from 200MHz to 2GHz.
The number of levels is not related to the CPU design; it's a function of the physical implementation on a given silicon process technology node.
In general more levels gives you more fine grained control over matching the required performance against one of the available levels, which should allow you to be more energy efficient. For example if you have an implementation with only two levels, 50% frequency and 100% frequency, then an application needing 55% CPU would have to run at 100% frequency with the loss in efficiency due to higher operating voltage that implies. The downside is that adding more levels is more complex to build in terms of voltage regulation and testing.
HTH, Pete
What does ARM guarantee when you sell a design ? The highest and lowest frequencies/voltage levels at which the design works for a particular technology ? And everything in between is left to the implementation ? You don't even suggest any guidelines ?
Basically, the motivation for my question came from observing two designs.
1) The ARM A9 on the OMAP4430 from TI based on 45nm. This one has 4 DVFS levels.
2) The ARM A15 on the Samsung Exynos 5422 based on 28nm. This one has 19 DVFS levels.
We do of course provide guidance on what we expect, but on the whole it's entirely down to the silicon implementation, as different partners will want to achieve different things for their designs to suit their target market.
Even on any one process node it is possible to move the eventual performance/power/area characteristics around significantly depending what a given SoC wants to achieve (lower static power, lower dynamic power, smaller area, faster frequency, etc) just by altering the choices of transistors used.
Cheers, Pete