When a interrupt occurs, ARM documentation(http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/3682.html) says interrupt is disabled till the very end of handlers. When the ARM documentation says that the processor automatically disables the single "Normal IRQ" interrupt, is it the case that all interrupts mapped (via the ARM Interrupt Controller) to the single IRQ gets disabled, or just the one interrupt which was raised is disabled ?
There is no SPSR in Cortex-M. The PSR and a number of registers are being pushed to the stack automatically at exception entry sequences so there is no need to disable interrupts. This is different from ARM7TDMI whuch dont have hardware stacking.
Regards,
Joseph
Sent from my Samsung device
I agree with you jyiu that CORTEX-M does not have SPSR register. Since I am currently reading lot of ARM documents to understand the architecture as a whole, I request you to mention as to what happens in case of CORTEX-A processor in the nested interrupt handler implementation since we have a SPSR in CORTEX-A processors. My understanding is interrupt is disabled for brief period to save the CPSR_IRQ to SPSR_SYS and also save the system mode registers before handling the new interrupt. Correct me If I am wrong.
Sorry for deviating from CORTEX-M to CORTEX-A, I am just curious about how interrupt is handled in ARM.