When a interrupt occurs, ARM documentation(http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/3682.html) says interrupt is disabled till the very end of handlers. When the ARM documentation says that the processor automatically disables the single "Normal IRQ" interrupt, is it the case that all interrupts mapped (via the ARM Interrupt Controller) to the single IRQ gets disabled, or just the one interrupt which was raised is disabled ?
Hello,
"Upon entry to the IRQ exception handler, the 'I' bit is set (of the CPSR)." means all IRQs are masked in the IRQ exception handler.
Best regards,
Yasuhiko Koumoto.
Very good and interesting question, msd - and a very good answer, yasuhikokoumoto.
jyiu once wrote that interrupts can be nested, thus an interrupt can be interrupted (even during the stacking event).
(see A Beginner’s Guide on Interrupt Latency - and Interrupt Latency of the ARM® Cortex®-M processors).
I would expect that SysTick is not considered an IRQ interrupt, so I perhaps SysTick is able to periodically trigger while inside an IRQ interurpt-handler. (jyiu, please correct me if I'm wrong here).
I think I might have seen the SysTick occur while inside another interrupt - but I am not 100% sure.
I guess the original question is related to classic ARM processors (e.g. ARM7TDMI). Newer Cortex-M processor support nested interrupts in its hardware.
I think so even in nested interrupts case, if interrupts are disabled for brief period to save the CPSR register. Correct me If I am wrong.
Sorry I will rephrase the question. I think so even in nested interrupts case, the interrupts are disabled for brief period to save the CPSR register to the SPSR. Correct me If I am wrong.
I'm a bit too rusty, when it comes to the pre-Cortex architectures, so the answers I would provide in this context would probably be something like "perhaps" or "perhaps not".
(I still miss some of the pre-Cortex features, though).
-So I will pass the question on to someone who can provide much better answers.
There is no SPSR in Cortex-M. The PSR and a number of registers are being pushed to the stack automatically at exception entry sequences so there is no need to disable interrupts. This is different from ARM7TDMI whuch dont have hardware stacking.
Regards,
Joseph
Sent from my Samsung device
I agree with you jyiu that CORTEX-M does not have SPSR register. Since I am currently reading lot of ARM documents to understand the architecture as a whole, I request you to mention as to what happens in case of CORTEX-A processor in the nested interrupt handler implementation since we have a SPSR in CORTEX-A processors. My understanding is interrupt is disabled for brief period to save the CPSR_IRQ to SPSR_SYS and also save the system mode registers before handling the new interrupt. Correct me If I am wrong.
Sorry for deviating from CORTEX-M to CORTEX-A, I am just curious about how interrupt is handled in ARM.